We talk a lot about process nodes at ExtremeTech, but we don’t often refer to exactly what a process node technically is. With Intel’s 10nm node now in production and TSMC + Samsung referring to future 5nm and 3nm nodes, it’s a great time to revisit the topic, specially the question of methods TSMC and Samsung compare to Intel.

Process nodes are typically named with a number accompanied by the abbreviation for nanometer: 32nm, 22nm, 14nm, etc. There is no fixed, objective relationship between any feature from the CPU and the name of the node. It was not always the situation. From roughly the 1960s with the end from the 1990s, nodes were named based on their gate lengths. This chart from IEEE shows the relationship:

For a long time, gate length (the size of the transistor gate) and half-pitch (half the length between two identical features on the chip) matched the procedure node name, however the last time this was true was 1997. The half-pitch continued to complement the node reputation for several generations but is not associated with it in any practical sense. In fact, it’s been many years since our geometric scaling of processor nodes actually matched using what the curve would look like if we’d been able to carry on actually shrinking feature sizes.

Well below 1nm before 2021? Pleasant fantasy.

If we’d hit the geometric scaling requirements to help keep node names and actual feature sizes synchronized, we’d have plunged below 1nm manufacturing six years back. The numbers that people use to indicate each new node are simply numbers that companies pick. In 2010, the ITRS (more about them in a moment) referred to the technology chum bucket dumped in at each node as enabling “equivalent scaling.” As we approach the end of the nanometer scale, companies may begin referring to angstroms rather than nanometers, or we may simply begin using decimal points. When I started operate in this industry it had been a lot more present with see journalists make reference to process nodes in microns instead of nanometers — 0.18-micron or 0.13-micron, for instance, rather than 180nm or 130nm.

How the marketplace Fragmented

Semiconductor manufacturing involves tremendous capital expenditure and a lot of long-term research. The typical period of time between whenever a new technological approach is introduced inside a paper and when it hits widescale commercial manufacturing is around the order of 10-15 years. Decades ago, the semiconductor industry recognized that it would be to everyone’s advantage if your general roadmap existed for node introductions and also the feature sizes those nodes would target. This could permit the broad, simultaneous development of all the bits of the puzzle necessary to bring a brand new node to promote. For many years, the ITRS — the International Technology Roadmap for Semiconductors — published an over-all roadmap for the industry. These roadmaps stretched over 15 years and set general targets for the semiconductor market.

Image by Wikipedia

The ITRS was published from 1998-2021. From 2021-2021, the ITRS reorganized in to the ITRS 2.0, but soon recognized the scope of their mandate — namely, to supply “the main reference in to the future for university, consortia, and industry researchers to stimulate innovation in a variety of regions of technology” required the organization to drastically expand its reach and coverage. The ITRS was retired and a new organization was formed called IRDS — International Roadmap for Devices and Systems — having a much larger mandate, covering a wider group of technologies.

This transfer of scope and focus mirrors what’s been happening across the foundry industry. The main reason we stopped tying gate length or half-pitch to node size is they either stopped scaling or began scaling much more slowly. As an alternative, companies have integrated various technology and manufacturing approaches to allow for continued node scaling. At 40/45nm, the likes of GF and TSMC introduced immersion lithography. Double-patterning was introduced at 32nm. Gate-last manufacturing would be a feature of 28nm. FinFETs were introduced by Intel at 22nm and the remaining industry at the 14/16nm node.

Companies sometimes introduce features and capabilities at different times. AMD and TSMC introduced immersion lithography at 40/45nm, but Intel waited until 32nm to use that technique, opting to roll out double-patterning first. GlobalFoundries and TSMC began using double-patterning more at 32/28nm. TSMC used gate-last construction at 28nm, while Samsung and GF used gate-first technology. But as progress has gotten slower, we’ve seen companies lean more heavily on marketing, having a greater array of defined “nodes.” Rather than waterfalling over a fairly large numerical space (90, 65, 45) the likes of Samsung are launching nodes that are right on surface of one another, numerically speaking:

One major difference between TSMC and Samsung at 3nm: Samsung will deploy GAAFETs (Gate-All-Around FETs), while TSMC continues using FinFETs for an additional generation.

I think you are able to reason that the product strategy isn’t clear, because there’s no way to tell which process nodes are evolved variants of earlier nodes if you don't possess the chart handy.

While node names aren't tied to any sort of feature size, and some features have stopped scaling, semiconductor manufacturers are still finding ways to enhance key metrics. That’s genuine engineering improvement. But because advantages are not as easy to come by now, and take longer to develop, information mill experimenting more using what to call those improvements. Samsung, for instance, is deploying a lot more node names of computer accustomed to. That’s marketing.

Why Do People Claim Intel 10nm and TSMC/Samsung 7nm Are Equivalent?

Because the manufacturing parameters for Intel’s 10nm process are very near to the values TSMC and Samsung use for what they call a 7nm process. The chart below is sucked from WikiChip, but it combines the known feature sizes for Intel’s 10nm node with the known feature sizes for TSMC’s and Samsung’s 7nm node. As you can tell, they’re very similar:

Image by ET, compiled from data at WikiChip

The delta 14nm / delta 10nm column shows how much each company scaled a particular feature down from its previous node. Intel and Samsung possess a tighter minimum metal pitch than TSMC does, but TSMC’s high-density SRAM cells are small compared to Intel’s, likely reflecting the needs of different customers in the Taiwanese foundry. Samsung’s cells, meanwhile, are even smaller than TSMC’s. Overall, however, Intel’s 10nm process hits most of the key metrics as what both TSMC and Samsung are calling 7nm.

Individual chips can always have features that depart from all of these sizes due to particular design goals. The information manufacturers provide on these numbers are for a typical expected implementation on a given node, not necessarily an exact match for any specific chip.

There happen to be questions regarding how closely Intel’s 10nm+ process (used for Ice Lake) reflects these figures (which I believe were published for Cannon Lake). It’s true that the expected specifications for Intel’s 10nm node might have changed slightly, but 14nm+ was an adjustment from 14nm too.

We don’t yet understand how Intel’s upcoming 7nm process will rival the 5nm and 3nm process nodes that'll be offered by TSMC and Samsung by the time Intel’s node is prepared. Intel has stated it wants to regain overall process leadership by 5nm. Best-case for that node launch is probably late 2024 – early 2025.

Pulling Everything Together

The best way to understand the meaning of a new process node would be to think of it as an umbrella term. When a foundry talks about rolling out a new process node, what they're saying boils down to this:

“We've made a new manufacturing process with smaller features and tighter tolerances. To have this goal, we have integrated new manufacturing technologies. We refer to this set of new manufacturing technologies like a process node because we want an umbrella term that enables us to capture the idea of progress and improved capability.”